1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
For a connection in a multi-layered wiring or between wiring layers, using copper (Cu) which is a low-resistance material, in a conventional semiconductor device, a method of manufacturing an embedded wiring structure by removing an unnecessary wiring material by a CMP technique is used (for example, Reference 1: Japanese Patent Laid-Open No. H9-306988). The embedded wiring is formed after forming a connecting plug from a lower wiring by a damascene method in which copper is embedded only in a wiring portion or a dual-damascene method in which wiring layers are connected to each other using copper in addition to embedding copper in the wiring portion. The dual-damascene method is described with reference to FIGS. 28A to 28E.
An insulating film 1002, a first wiring 1003, an interlayer insulating film 1004, an etching stopper insulating film 1005, and an interwiring insulating film 1006 are formed over a semiconductor substrate 1001 (FIG. 28A). A resist film 1007 provided with an opening portion is formed over the interwiring insulating film 1006, and a trench 1009 is formed in the interwiring insulating film 1006 using the resist film 1007 (FIG. 28B). After removing the resist film 1007, a resist film 1010 also having an opening portion is formed, and the etching stopper insulating film 1005 and the interlayer insulating film 1004 are etched to expose the first wiring using the resist film 1010 to form a connecting hole 1012 (FIG. 28C).
Copper 1023 is applied over the interwiring insulating film 1006, the connecting hole 1012, and the trench 1009 (FIG. 28D). The copper 1023 is removed in the part except the inside of the trench 1009 and connecting hole 1012 by polishing to form a connecting plug portion 1024 and a second wiring 1025 (FIG. 28E).